This invention relates to methods of processing ruthenium silicide.
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet, as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics, as well as the cell structure, are important.
Highly integrated memory devices are expected to require a very thin dielectric film for the three-dimensional capacitor of cylindrically stacked or trenched structures. To meet this requirement, and beyond, the capacitor dielectric thickness will be below 2.5 nm of SiO2 equivalent thickness. Chemical vapor deposited (CVD) high k dielectric materials, for example tantalum pentoxide, barium strontium titanate, barium titanate, lead zirconium titanate, strontium bismuth tantalate and others, are considered to be very promising cell dielectric layers for this purpose. The dielectric constants of these materials are typically three times or more greater than that of conventional Si3N4 based capacitor dielectric layers. However, one drawback associated with dielectric layers such as these is undesired leakage current characteristics. Accordingly, although these materials inherently have higher dielectric properties, as-deposited they typically produce unacceptable results due to excessive leakage current.
This is typically overcome by exposing such layers to extreme oxidizing conditions to result in significant densification. Undesirably, however, such has a tendency to form a SiO2 layer intermediate or between the lower electrode (typically a metal in a metal-insulator-metal capacitor) and an underlying lower electrode connection (typical polysilicon).
One prior art technique of addressing this problem is to form a conductive barrier layer, for example ruthenium silicide, intermediate the lower silicon material and the metal electrode. A preferred technique for forming a ruthenium silicide barrier layer is by CVD. However, the CVD process typically also deposits ruthenium silicide on the edges and backside of the wafer. This excess ruthenium silicide might be dislodged in later processing, and is accordingly desirably removed from the substrate surface at some point after processing the ruthenium silicide on the wafer front side and passing the wafer to further processing steps. Unfortunately, ruthenium silicide is presently a very difficult material to remove from the substrate by chemical etching. Accordingly, it has heretofore been very difficult to remove ruthenium silicide from the backside of semiconductor substrates to effectively suitable low levels to preclude or reduce significant risks of subsequent contamination.
The invention includes methods of processing ruthenium silicide. In one implementation, a ruthenium silicide processing method sequentially includes forming ruthenium silicide over front and back sides of a semiconductor substrate. The backside ruthenium silicide is exposed to a chlorine and fluorine containing aqueous solution effective to remove at least some ruthenium silicide therefrom. Then, the substrate backside is exposed to an aqueous ruthenium oxide etchant solution. Then, the substrate backside is exposed to an aqueous hydrofluoric acid containing solution.